A/D Data Register (Adcr0, Adcr1) - Fujitsu MB90390 Series Hardware Manual

CHAPTER 18 8/10-BIT A/D CONVERTER
18.4.4

A/D Data Register (ADCR0, ADCR1)

The A/D data register (ADCR0, ADCR1) holds the result of A/D conversion and selects
the resolution of A/D conversion.
■ A/D Data Register (ADCR0, ADCR1)
bit15 bit14 bit13
Address
00003 7
H
S10 ST1
00003 6
H
W W
R : Read only
W : Write only
X : Undefined value
- : Undefined
Note:
When setting the Comparison and Sampling time, the minimal required value has to be respected.
For example, 44 machine cycles cannot be used with some frequencies. Please see the Data sheet
for the precise specification.
292
Figure 18.4-6 A/D Data Register (ADCR0, ADCR1)
bit12 bit11 bit10 bit9
ST0 CT1 CT0 - D9
W W W - R
bit8 bit7 bit6 bit5 bit4
D8 D7 D6 D5 D4
R R R R R
D0 to D9
Conversion data
CT1 CT0
0 0
44 machine cycles (5.50µs@8MHz)
1
0
66 machine cycles (3.3µs@20MHz)
1 0
88 machine cycles (3.67µs@24MHz)
1 1
176 machine cycles (7.33µs@24MHz)
Sampling time setting bit
ST1 ST0
0 0 20 machine cycles (2.5µs@8MHz)
0 1 32 machine cycles (1.6µs@20MHz)
1 0 48 machine cycles (2.0µs@24MHz)
1 1 128 machine cycles (5.33µs@24MHz)
S10
10-bit resolution mode (D9 to D0)
0
8-bit resolution mode (D7 to D0)
1
bit3 bit2 bit1 bit0
Initial value
D3 D2 D1 D0
00000XXX
R R R R
XXXXXXXX
AD data bit
Comparison time setting bit
AD data bit
B
B