Status Register (Usr) - Fujitsu MB90390 Series Hardware Manual

19.3.2

Status Register (USR)

USR indicates the current state of the UART0, UART1 port.
■ Status Register (USR)
Address:
bit 15
ch.0 000021
H
RDRF
ch.1 000025
H
R/W
R
Figure 19.3-2 Configuration of the Status Register (USR)
14 13 12 11 10
PE RIE TIE RBF
ORFE TDRE
R R R R R/W R/W
: Readable and writable
: Flag is read only, write to it has
no effect
: Initial value
9 8
USR0 USR1
Initial value
TBF
0 0 0 1 0 0 0 0
B
R R
bit8
TBF
0 Transmitter idle
1 Transmitter busy
bit9
RBF
0 Receiver idle
1 Receiver busy
bit10
TIE
0 Disable interrupt
1 Enable interrupt
bit11
RIE
0 Disable interrupt
1 Enable interrupt
bit12
TDRE
0 Data present in UODR0, UODR1
1 No data in UODR0, UODR1
bit13
PE
0 No parity error occurred
1 Parity error occurred
bit14
ORFE
0 No overrun/framing error occurred
1 An overrun/framing error occurred during reception
bit15
RDRF
0 No data in UIDR0, UIDR1
1 Data present in UIDR0, UIDR1
CHAPTER 19 UART0, UART1
Transmission busy flag bit
Receiver busy flag bit
Transmission interrupt enable bit
Reception interrupt enable bit
Transmission data register empty bit
Parity error bit
Overrun/Framing error bit
Reception data register full
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