Low-Power Consumption Mode Control Register (Lpmcr) - Fujitsu MB90390 Series Hardware Manual

8.3

Low-Power Consumption Mode Control Register (LPMCR)

This register switches to or releases the low-power consumption mode. This register
also sets the number of CPU clock pulses to halt during the CPU intermittent operation
mode.
■ Low-power Consumption Mode Control Register (LPMCR)
Figure 8.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Figure 8.3-1 Configuration of the Low-power Consumption Mode Control Register (LPMCR)
bit15
Address:
(CKSCR)
0000A0
H
Readable and writable
R/W :
W : Write only
: Initial value
bit7 bit6 bit5 bit4 bit3
STP SLP SPL RST TMD
W W R/W W R/W
Reserved
0
CG1 CG0
0 0
0 1
1 0
1 1
TMD
0 Switches to the time-base timer mode
1
No change, no effect on operation
RST
0 Generates an internal reset signal of three machine cycles.
1 No change, no effect on operation
SPL
Retained
0
1 High impedance
SLP
0
No change, no effect on operation
Switches to sleep mode.
1
STP
No change, no effect on operation
0
1 Switches to stop mode.
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Initial value
bit2 bit1
bit0
Re-
CG1 CG0
00011000
served
R/W R/W R/W
Reserved bit
Always write "0" to this bit
Count bit for CPU clock temporary halt cycle
0 cycles (CPU clock = Resource clock)
8 cycles (CPU clock: Resource clock =1:3 to 4 approx.)
16 cycles (CPU clock: Resource clock = 1:5 to 6 approx.)
32 cycles (CPU clock: Resource clock = 1:9 to 10 approx.)
Time-base timer mode bit
Internal reset signal generation bit
Pin state setting bit
(for time-base timer mode and stop mode)
Sleep mode bit
Stop mode bit
B
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