Fujitsu MB90390 Series Hardware Manual page 162

CHAPTER 7 RESETS
■ Correspondence between Reset Cause Bits and Reset Causes
Figure 7.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC).
Table 7.5-1 maps the correspondence between the reset cause bits and reset causes. See Table 12.1-2 in
Section "12.1 Outline of Watchdog Timer", for details.
Figure 7.5-2 Configuration of Reset Cause Bits (Watchdog Timer Control Register)
Watchdog timer control register (WDTC)
Address:
0000A8
R : Read only
W : Write only
X : Undefined
Table 7.5-1 Correspondence between Reset Cause Bits and Reset Causes
Power-on reset
Watchdog timer overflow
External reset request via RST pin
Software reset request
*: Previous state defined
X: Undefined
■ Notes about Reset Cause Bits
●
Multiple reset causes generated at the same time
When multiple reset causes are generated at the same time, the corresponding reset cause bits of the
watchdog timer control register (WDTC) are also set to "1". If, for example, an external reset request via
the RST pin and the watchdog timer overflow occur at the same time, the ERST and the WRST bits are
both set to "1".
●
Power-on reset
For a power-on reset, because the PONR bit is set to "1" but all other reset cause bits are undefined, the
software should be programmed so that it will ignore all reset cause bits except the PONR bit if it is "1".
134
bit15 bit8 bit7
PONR
(TBTC)
H
R
Reset cause
bit6 bit5 bit4 bit3 bit2
WTE WT1 WT0
- WRST ERST SRST
R R R W
-
PONR WRST
1 X
* 1
* *
* *
bit1 bit0
Initial value
X - X X X X X
B
W W
ERST SRST
X
*
1
*
X
*
*
1