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CHAPTER 5 CLOCKS
Clock generation block
X0
Pin
System
clock
generation
X1
circuit
Pin
HCLK : Oscillation clock
MCLK : Main clock
PCLK : PLL clock
φ
: Machine clock
φ
: CAN0 to CAN4 clock
C
88
Figure 5.1-1 Clock Supply Map
MCS
Time-base timer
bit
1 2 3 4 6 8
PLL multiplier circuit
PCLK
Clock Selector
Clock Modulator
Clock Selector
Divide-
by-2
HCLK
MCLK
Peripheral function
4
Watchdog timer
8/16-bit PPG
8/16-bit PPG
CAN0 to CAN4
16-bit reload
timer 0/1
φ
UART0/UART1/
C
UART2(UART/3)
φ
10-bit ADC
Sound Generator
16-bit free-run
timer 0/1
CPU
16-bit input capture
Output compare
SMC (6 ch)
3
Oscillation stabiliza-
tion wait control
2
Note: I
C Interface is optional and not shown in this diagram
PPG00 to PPG05
Pin
PPG10 to PPG15
Pin
RX/TX
Pins
TIN0/TIN1
Pins
TOUT0/TOUT1
Pins
SIN0/SIN1/SIN2/(SIN3)
Pins
...
SOT0/SOT1/SOT2/(SOT3)
+
Pins
...
Serial I/O
SCK0/SCK1/SCK2/(SCK3)
Pins
...
AN0 to AN14
Pins
...
(15 ch)
SGO
Pin
SGA
Pin
FRCK0/FRCK1
Pins
IN0 to IN5
...
Pins
(6 ch)
OUT0 to OUT7
Pins
...
(8 ch)
PWM pins
Pin
...
DVxx pins
Pin
...
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