Fujitsu MB90390 Series Hardware Manual page 506

CHAPTER 23 CAN CONTROLLER
■ Prescaler Settings
Figure 23.6-7 shows the bit time segment in CAN specification, Figure 23.6-8 shows the bit time
segment in CAN controller.
The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS1.0, and RSJ =
RSJ1 and RSJ0 when the input clock (CLK), time quanta (TQ), bit time (BT), synchronous segment
(SYNC_SEG), time segment 1 and 2 (TSEG1 and TSEG2), and resynchronization jump width [(RSJ1 and
RSJ0) +1] frequency division is shown below.
The input clock is supplied with the machine clock.
For correct operation, the following conditions should be met.
In order to meet the bit timing requirements defined in the CAN specification, additions have to be met,
e.g. the propagation delay has to be considered.
478
Figure 23.6-7 Bit Time Segment in CAN Specification
Nominal bit time
SYNC_SEG PROP_SEG
Figure 23.6-8 Bit Time Segment in CAN Controller
Nominal bit time
SYNC_SEG
TQ
BT
RSJW = (RSJ + 1) x TQ
PHASE_SEG1 PHASE_SEG2
Sample point
TSEG1 TSEG2
Sample point
= (PSC + 1) x CLK
= SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1) + (TS2 +1)) x TQ
= (3 + TS1 +TS2) x TQ
For 1 PSC 63:
TSEG1 2TQ
TSEG1 RSJW
TSEG2 2TQ
TSEG2 RSJW
For PSC = 0:
TSEG1 5TQ
TSEG2 2TQ
TSEG2 RSJW