Fujitsu MB90390 Series Hardware Manual page 726

Block Diagram of
MB90394HA/MB90F394H(A) ................. 8
Block Diagram of MB90V390H ............................ 6
Block Diagram of
MB90V390HA/MB90V390HB ................ 7
Block Diagram of ROM Mirroring Module......... 552
Block Diagram of Sound Generator ................... 534
Block Diagram of Stepping Motor
Controller ........................................... 522
Block Diagram of the 8/10-bit A/D
Converter ........................................... 282
Block Diagram of the Address Match Detection
Function ............................................. 544
Block Diagram of the Clock Generation
Block ................................................... 89
Block Diagram of the Entire Flash Memory........ 557
Block Diagram of the Low-power Consumption
Control Circuit .................................... 141
Block Diagram of Time-base Timer ................... 178
Block Diagram of UART2, UART3 ................... 342
Block Diagram of Watch Timer......................... 238
Block Diagrams of the 8/10-bit A/D Converter
Pins.................................................... 285
Block Diagrams of the External Reset Pin .......... 130
Input Capture Block Diagram ............................ 215
Serial I/O Block Diagram.................................. 438
UART0, UART1 Block Diagram....................... 313
Watchdog Timer Block Diagram ....................... 184
BTR
Bit Timing Register (BTR)................................ 477
Bit Timing Register (BTR) Contents .................. 477
Buffer Address Pointer
Buffer Address Pointer (BAP) ............................. 74
Bus Control Register
Bus Control Register (IBCR)............................. 413
Bus Mode Setting Bits
Bus Mode Setting Bits ...................................... 166
Bus Operation
Conditions for Canceling Bus Operation Stop
(HALT=0) .......................................... 472
Conditions for Setting Bus Operation Stop
(HALT=1) .......................................... 472
State during Bus Operation Stop (HALT=1) ....... 473
Bus Status Register
Bus Status Register (IBSR) ............................... 410
BVAL
For Non-H Devices,e.q. MB90V390: Caution for
Disabling Message Buffers by BVAL
Bits .................................................... 520
BVALR
Message Buffer Valid Register (BVALR)........... 479
C
Calculating
Calculating the Execution Cycle Count .............. 640
698
CAN Controller
Block Diagram of CAN Controller .................... 457
Canceling a Transmission Request from the CAN
Controller........................................... 501
Features of CAN Controller .............................. 456
Reception Flowchart of the CAN Controller ....... 507
Starting Transmission of the CAN Controller ..... 501
Transmission Flowchart of the CAN
Controller........................................... 503
CAN Direct Mode Register
CAN Direct Mode Register (CDMR) ................. 518
CAN Direct Mode Register Contents ................. 518
CAN Switch Register
CAN Switch Register (CANSWR) Contents....... 516
CAN2 RX/TX Pin Switching Register
CAN2 RX/TX Pin Switching Register
(CANSWR)........................................ 516
CANSWR
CAN Switch Register (CANSWR) Contents....... 516
CAN2 RX/TX Pin Switching Register
(CANSWR)........................................ 516
CCR
Condition Code Register (CCR) .......................... 41
CDCR
Serial I/O Prescaler (CDCR) ............................. 445
CDMR
CAN Direct Mode Register (CDMR) ................. 518
CE Control
Write,Data Polling,Read (CE Control) ............... 684
Chip Erase
Chip Erase/Sector Erase Command
Sequence............................................ 685
CKSCR
Configuration of the Clock Selection Register
(CKSCR) ............................................. 92
CLK Asynchronous Baud Rate
CLK Asynchronous Baud Rate.......................... 324
CLK Synchronous Baud Rate
CLK Synchronous Baud Rate............................ 323
Clock
Clocks .............................................................. 86
Clock Frequency
Oscillating Clock Frequency and Serial Clock Input
Frequency .......................................... 595
Clock Generation Block
Block Diagram of the Clock Generation
Block ................................................... 89
Clock Mode
Clock Mode..................................................... 139
Clock Mode Switching ..................................... 160
Clock Mode Transition ....................................... 97
Clock Modulator
Clock Modulator................................................ 98
Clock Modulator Registers ............................... 107