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CHAPTER 21 400 kHz I
■ SCC, MSS and INT Bit Competition
Simultaneously writing to the SCC, MSS and INT bits causes a competition to transfer the next byte, to
generate a repeated start condition or to generate a stop condition. In these cases the order of priority is as
follows:
• Next byte transfer and stop condition generation.
When "0" is written to the INT bit and "0" is written to the MSS bit, the MSS bit takes priority and a
stop condition is generated.
• Next byte transfer and start condition generation.
When "0" is written to the INT bit and "1" is written to the SCC bit, the SCC bit takes priority. A
repeated start condition is generated and the contents of the IDAR register is sent.
• Repeated start condition generation and stop condition generation.
When a "1" is written to the SCC bit and "0" to the MSS bit, the MSS bit clearing takes priority. A stop
condition is generated and the interface enters slave mode.
Notes:
• Note on using MB90F394H(A), MB90V390H only.
If there are some other master mode LSIs on the bus, the device can not be used as the master
mode.
- Example of usable configuration
- Example of unusable configuration
418
2
C INTERFACE
MB90F394H
MB90V390H
Master
MB90F394H
MB90V390H
Slave
MB90F394H
MB90V390H
Master
Slave B
Slave A
Slave A
Master A
Master A
Slave A
2
I
C bus
2
I
C bus
2
I
C bus
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