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23.6.12
Transmission Complete Register (TCR)
At completion of transmission by the message buffer (x), the corresponding TCx
becomes "1".
If TIEx of the transmission complete interrupt enable register (TIER) is "1", an interrupt
occurs.
■ Transmission Complete Register (TCR)
Figure 23.6-15 Configuration of the Transmission Complete Register (TCR)
Address:
CAN0: 000077
CAN1: 000087
CAN2: 003577
CAN3: 003587
CAN4: 003597
Address:
CAN0: 000076
CAN1: 000086
CAN2: 003576
CAN3: 003586
CAN4: 003596
[bit15 to bit0] TC15 to TC0:
●
Conditions for TCx = 0
• Write "0" to TCx.
• Write "1" to TREQx of the transmission request register (TREQR).
After the completion of transmission, write "0" to TCx to set it to "0". Writing "1" to TCx is ignored.
"1" is read when a Read Modify Write (RMW) instruction is performed.
Note:
If setting to "1" by completion of the transmit operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
bit
15
14
13
12
11
H
TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8
H
H
R/W R/W R/W R/W
R/W
H
H
7
6
5
4
3
bit
H
TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
H
H
R/W R/W R/W R/W
R/W
H
H
CHAPTER 23 CAN CONTROLLER
10
9
8
TCRn (upper)
Initial value
0 0 0 0 0 0 0 0
R/W
R/W R/W
2
1
0
TCRn (lower)
Initial value
0 0 0 0 0 0 0 0
R/W
R/W R/W
B
B
n = 0, 1, 2, 3, 4
485
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