Usage Notes On Low-Power Consumption Mode - Fujitsu MB90390 Series Hardware Manual

8.8

Usage Notes on Low-Power Consumption Mode

Note the following four items when using the low-power consumption mode:
• Switching to a standby mode and interrupt
• Notes on the transition to standby mode
• Release of a standby mode by an interrupt
• Release of the stop mode
• Oscillation stabilization wait time
• Switching to the clock modes
• Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to
Enter the Standby Mode
■ Switching to a Standby Mode and Interrupt
During an interrupt request to the CPU from a peripheral function, the CPU ignores the setting of the low-
power consumption mode control register (LPMCR) even if "1" is written to the STP and SLP bits or if "0"
is written to the TMD bit. Thus, switching to each standby mode is disabled (even after processing of the
interrupt is completed, there is no switch to a standby mode). If the interrupt level is seven or a higher
priority, this action does not depend on whether the interrupt request is accepted by the CPU. However,
during execution of interrupt processing by the CPU, if the interrupt request flag for the interrupt is cleared
and no other interrupt requests have been issued, switching to a standby mode can be performed.
■ Notes on the Transition to Standby Mode
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or
time-base timer mode, use the following procedure:
• Disable the output of peripheral functions.
• Set the SPL bit to "1", STP bit to "1", or TMD bit to "0" in the low-power mode control register
(LPMCR).
■ Release of the Standby Mode by an Interrupt
If an interrupt request of interrupt level seven or a higher priority is issued from a peripheral function
during the sleep, time-base timer, or stop mode, the standby mode is released, which does not depend on
whether the CPU accepts the interrupt.
After the release of the standby mode by an interrupt, normal processing is performed. The CPU branches
to the interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt
level setting bits (IL2, IL1, and IL0 of ICR) is higher than the interrupt level mask register (ILM) and the
interrupt enable flag (I) of the condition code register (CCR) is set to "1" (enabled).
If the interrupt is not accepted, the CPU starts the execution with the instruction following the instruction in
which switching to the standby mode has been specified.
When interrupt processing is executed normally, the CPU first executes the instruction following the
instruction in which switching to the standby mode has been specified. The CPU then proceeds to interrupt
processing. Depending on the condition when switching to a standby mode was performed, however, the
CPU may proceed to interrupt processing before executing the next instruction.
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
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