Fujitsu MB90390 Series Hardware Manual page 183

RST pin
Stop mode
Main clock
PLL clock
CPU clock
CPU operation
Notes:
• To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode, disable the output of peripheral functions, and set the STP bit of the low-power
consumption mode control register (LPMCR) to "1".
This applies to the following pins:
P03/IN3/OUT6, P05/IN5/OUT7, P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4,
P13/OUT5, P15/TOT0, P16/SGO, P17/SGA, P20/TX1, P31/TX0, P33/TOT1, P34/SOT0, P35/
SCK0
• In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL
stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock
oscillation stabilization wait time. The oscillation stabilization wait times for the main clock and
PLL clock are counted simultaneously according to the value specified in the oscillation
stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The
oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register
must be selected accordingly to account for the longer of main clock and PLL clock oscillation
stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 2
HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the
clock selection register to "10
Figure 8.5-2 Release of the Stop Mode (External Reset)
Inactive
Stop mode released.
" or "11
B
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Oscillation stabilization wait
Oscillating
Inactive
Inactive Reset sequence Execution
Reset released.
".
B
Oscillating
Main clock
14
/
155