Sleep Mode - Fujitsu MB90390 Series Hardware Manual

8.5.1

Sleep Mode

This mode causes the CPU operating clock to stop while other components continue to
operate. When the low-power consumption mode control register (LPMCR) indicates a
switch to a sleep mode, a switch to the PLL sleep mode occurs if the PLL clock mode
has been set. A switch to the main sleep mode occurs if the main clock mode has been
set.
■ Switching to Sleep Mode
Writing "1" in the SLP bit and the TMD bit and "0" in the STP bit of the low-power consumption mode
control register (LPMCR) triggers a switch to a sleep mode. At this time, if the MSC bit is "0" in the clock
selection register (CKSCR), a switch to the PLL sleep mode is triggered. If the MSC bit is "1", a switch to
the main sleep mode is triggered.
Note:
When "1" is written to the SLP and STP bits at the same time, the STP bit setting overrides the SLP
bit setting and the mode switches to the stop mode. When "1" is written to the SLP bit and "0" is
written to the TMD bit at the same time, the TMD bit setting overrides the SLP bit setting and the
mode switches to the time-base timer mode.
●
Data retention function
In a sleep mode, the contents of dedicated registers, such as accumulators, and the built-in RAM are
retained.
●
Operation during an interrupt request
Writing "1" in the SLP bit of the low-power consumption mode control register during an interrupt request
does not trigger a switch to a sleep mode. If the CPU does not accept the interrupt, the CPU executes the
next instruction. If the CPU accepts the interrupt, CPU operation immediately branches to the interrupt
processing routine.
●
Status of pins
During a sleep mode, all pins (excluding those used for bus I/O or bus control) retain their previous status.
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
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