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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.5
Standby Mode
The standby mode includes the sleep (PLL sleep, main sleep), time-base timer, and stop
modes.
■ Operation Status During Standby Mode
Table 8.5-1 shows operation statuses during standby mode.
Table 8.5-1 Operation Status During Standby Mode
Standby mode
PLL sleep
mode
Sleep
mode
Main sleep
mode
Time-base
timer mode
Time-
(SPL=0)
base timer
Time-base
mode
timer mode
(SPL=1)
Stop mode
(SPL=0)
Stop
mode
Stop mode
(SPL=1)
*: The time-base timer and watch timer operate.
SPL:
Pin state setting bit of low-power consumption mode control register (LPMCR)
SLP:
Sleep mode bit of low-power consumption mode control register (LPMCR)
STP:
Stop mode bit of low-power consumption mode control register (LPMCR)
TMD:
Time-base timer mode bit of low-power consumption mode control register (LPMCR)
MCS:
Machine clock selection bit of clock selection register (CKSCR)
Hi-Z:
High-impedance
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode or time-base timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to "1" or set the TMD bit to "0".
This applies to the following pins:
P03/IN3/OUT6, P05/IN5/OUT7, P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4,
P13/OUT5, P15/TOT0, P16/SGO, P17/SGA, P20/TX1, P31/TX0, P33/TOT1, P34/SOT0, P35/SCK0
148
Condition
Main
for switch
clock
MCS=0
Active
SLP=1
MCS=1
Active
SLP=1
TMD=0
Active
TMD=0
STP=1
Inactive
STP=1
Machine
CPU
clock
Active
Inactive
Inactive
Peripheral
Pin
Active
Active
Retained
*
Inactive
Hi-Z
Retained
Inactive
Hi-Z
Release
event
Reset
or
Interrupt
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