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CHAPTER 23 CAN CONTROLLER
■ For Non-H Devices, e.q. MB90V390: Caution for Disabling Message Buffers by BVAL Bits
The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled
while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is "0"
and CAN Controller is ready to receive or transmit messages). This section shows the work around of this
malfunction.
●
Condition
When following two conditions occur at the same time, the CAN Controller will not perform to receive or
transmit messages normally.
• CAN Controller is participating in the CAN communication. (i.e. the read value of the CSR: HALT bit
is "0" and CAN Controller is ready to receive or transmit messages)
• Message buffers are read or written when BVAL bits disable the message buffers.
●
Work around
Operation for re-configuring receiving message buffers
While CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is
"0" and CAN Controller is ready to receive or transmit messages), it is necessary to follow one from the
two operations described below to re-configure message buffers by ID, AMS and AMR0/AMR1
register settings.
• Use of HALT bit
- Write "1" to HALT bit and read it back for checking the result is "1". Then change the settings for
ID/AMS/AMR0/AMR1 registers.
• No Use of Message Buffer 0
- Do not use the message buffer 0. In other words, disable message buffer (BVAL0=0), prohibit
receive interrupt (RIE0=0) and do not request transmission (TREQ0=0).
Operation for processing received message
Do not use the receiving prohibition by BVAL bit to avoid over-written of next message. Use the
ROVR bit for checking if over-write has been performed. For details, refer to Sections "23.6.16
Receive Overrun Register (ROVRR)" and "23.12 Procedure for Reception by Message Buffer (x)".
Operation for suppressing transmission request
Do not use BVAL bit for suppressing transmission request, use TCAN bit instead of it.
Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to
change contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking
if TREQ bit is "0" or after completion of the previous message transmission (TC=1).
In case a buffer needs to be disabled, ensure that no transmission request is pending (if it was requested
before)! Therefore, do not reset BVALx-Bit before testing, if a transmission is ongoing:
a) Cancel the transmission request (TCANx=1;), if necessary
b) and wait for the transmission completion (while (TREQx==1);) by polling or interrupt.
Only after that the transmission buffer can be disabled (BVALx=0;).
Note for case a), if transmission of that buffer has already started, canceling the request is ignored and
disabling the buffer is delayed until the end of the transmission.
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