Reception Complete Register (Rcr) - Fujitsu MB90390 Series Hardware Manual

23.6.14

Reception Complete Register (RCR)

At completion of storing received message in the message buffer (x), RCx becomes "1".
If RIEx of the reception complete interrupt enable register (RIER) is "1", an interrupt
occurs.
■ Reception Complete Register (RCR)
Figure 23.6-17 Configuration of the Reception Complete Register (RCR)
Address:
CAN0: 000079
CAN1: 000089
CAN2: 003579
CAN3: 003589
CAN4: 003599
Address:
CAN0: 000078
CAN1: 000088
CAN2: 003578
CAN3: 003588
CAN4: 003598
[bit15 to bit0] RC15 to RC0:
●
Conditions for RCx = 0
Write "0" to RCx.
After completion of handling received message, write "0" to RCx to set it to "0". Writing "1" to RCx is
ignored.
"1" is read when a Read Modify Write (RMW) instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
15 14 13 12 11
H
RC15 RC14 RC13 RC12 RC11 RC10 RC9
H
H
R/W R/W R/W R/W R/W
H
H
bit 7 6 5 4 3
H
RC5 RC4 RC3
RC7 RC6
H
H
R/W R/W R/W R/W R/W
H
H
CHAPTER 23 CAN CONTROLLER
10 9 8
RCRn (upper)
RC8
Initial value
0 0 0 0 0 0 0 0
R/W R/W R/W
2 1 0
RCRn (lower)
RC2 RC1 RC0
Initial value
0 0 0 0 0 0 0 0
R/W R/W R/W
B
B
n = 0, 1, 2, 3, 4
487