Fujitsu MB90390 Series Hardware Manual page 449

A sample flow is given below.
Set the MSS bit in the bus control register (IBCR) to "1".
Wait * for the time of three-bit data transmission at the I
transfer frequency set in the clock control register (ICCR).
*: When "arbitration lost" is detected, the MSS bit is set to "1" and then the AL bit is set to
"1" without fail after the time for three-bit data transmission at the I
- Example of occurrence for an interrupt (INT bit = 1) upon detection of "AL bit = 1"
When an instruction which generates a start condition is executed (setting the MSS bit to 1)
with "bus busy" detected (BB bit = 1) and arbitration is lost, the INT bit interrupt occurs upon
detection of "AL bit = 1".
Figure 21.2-5 Diagram of Timing at which an Interrupt Upon Detection of " AL Bit = 1 " Occurs
Start Condition
SCL pin
SDA pin
EN bit
MSS bit
AL bit
BB bit
INT bit
Master mode setting
BB bit = 0 and AL bit = 1 ?
YES
Set the EN bit to "0" to initialize I
Interrupt in the ninth clock cycle
SLAVE ADDRESS
CHAPTER 21 400 kHz I
2
C
NO
to normal process
2
C
ACK DAT
Clearing the AL bit
by software
Releasing the SCL by clearing
the INT bit by software
2
C INTERFACE
2
C transfer frequency.
421