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■ Interrupt Level Mask Register (ILM)
The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is
accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the
highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-1). Therefore, for an
interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is
accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the same or lower level cannot
be accepted subsequently. ILM is initialized to all zeroes by a reset. An instruction may transfer an eight-bit
immediate value to the ILM register, but only the low-order three bits of that data are used.
Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register
ILM2
ILM1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Figure 2.7-9 Interrupt Level Register (ILM)
I L M 2
I L M 1
0
Initial value
ILM0
Level value
0
0
1
1
0
2
1
3
0
4
1
5
0
6
1
7
ILM
I L M 0
0
0
Acceptable interrupt level
Interrupt disabled
Level value smaller than 1
Level value smaller than 2
Level value smaller than 3
Level value smaller than 4
Level value smaller than 5
Level value smaller than 6
CHAPTER 2 CPU
0 only
43
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