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20.5
UART2, UART3 Interrupts
UART2, UART3 uses both reception and transmission interrupts. An interrupt request
can be generated for either of the following causes:
• Receive data is set in the Reception Data Register (RDR2/RDR3), or a reception error
occurs.
• Transmission data is transferred from the Transmission Data Register (TDR2/TDR3) to
the transmission shift register and started.
• A LIN synch break is detected
The extended intelligent I/O service (EI
■ LIN-UART2, UART3 Interrupts
Table 20.5-1 lists the interrupt control bits and interrupt causes of LIN-UART2, UART3.
Table 20.5-1 Interrupt Control Bits and Interrupt Causes of LIN-UART2, UART3
Reception/
Interrupt
transmission/
request
ICU
flag bit
RDRF
ORE
Reception
FRE
PE
LBD
Transmission
TDRE
ICP1/
ICP3/
ICP5
Input Capture
Unit
ICP1/
ICP3/
ICP5
❍: Used
x: Unused
*: Only available if ECCR2/ECCR3:SSM = 1
Operation
Flag
mode
Register
0
1
2
❍ ❍ ❍ ❍
SSR2/SSR3
❍ ❍ ❍ ❍ Overrun error
SSR2/SSR3
❍ ❍ *
SSR2/SSR3
❍ x
SSR2/SSR3
*
ESCR2/
x
x
x
ESCR3
❍ ❍ ❍ ❍
SSR2/SSR3
ICS01/
ICS23/
x
x
x
ICS45
ICS01/
ICS23/
x
x
x
ICS45
2
OS) is available for these interrupts.
Interrupt
Interrupt
cause
cause
enable bit
3
receive data is
written to
RDR2/RDR3
SSR2/
SSR3: RIE
❍ Framing error
x
Parity error
ESCR2/
LIN synch
❍
ESCR3:
break detected
LBIE
TDR2/TDR3
SSR2/
empty
SSR3: TIE
1st falling edge
ICS01/
❍
of LIN synch
ICS23/
field
ICS45:
ICE1/
5th falling edge
ICE3/
❍
of LIN synch
ICE5
field
CHAPTER 20 UART2, UART3
How to clear the Interrupt
Request
Receive data is read.
MB90V390H/MB90F394H(A):
LIN synch break is detected
(LBD = 1).
"1" is written to clear rec. error bit
(SCR2/3:CRE).
MB90V390H/MB90F394H(A):
LIN synch break is detected
(LBD = 1).
"0" is written to ESCR2/ESCR3:
LBD
Writing transmission data and 1
writing in LIN Synch break
generation bit (ECCR2/ECCR3:
LBR)
disable ICP1/ICP3/ICP5
365
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