Fujitsu MB90390 Series Hardware Manual page 26

Reference: Main changes (Rev.2 → Rev.3)
Page
Figure 20.7-16 Settings for UART2, UART3 in Operation Mode 3 (LIN)
Mode3 of EXT is changed.
→ 0)
(
398 Mode3 of SCKE is changed.
→ 0)
(
Mode3 of SCES is changed.
(0 → +)
Figure 20.7-18 UART2, UART3 LIN Master Flow Chart is changed.
399
(RXE=0, RIE=1 → RXE=1, RIE=1)
● Enabling operations is changed.
401
(control register (SCR3) → serial control register (SCR2/SCR3))
■ I 2
C Interface Registers is changed.
(ITBA → ITBAH)
(ITBA → ITBAL)
408, 409
(ITMK → ITMKH)
(ITMK → ITMKL)
(Figure is added in Noise filter configuration register (INFCR))
Table 21.2-3 Function of Each Bit of the Ten Bit Slave Address Register (ITBA)
422 Bit name of bit9 to bit0 is changed.
(TBA9 to 0 → TA9 to TA0)
■ Ten Bit Address Mask Register (ITMK) is changed.
(ITMK → ITMKH)
423
(ITMK → ITMKL)
Table 21.2-6 Function of Each Bit of the I
426
Bit name of bit14 to bit8 is changed.
(SMK → SM6 to SM0)
Table 21.2-8 Function of Each Bit of the I
Function of bit14 is changed.
429
Function of bit13 is changed.
(Notes is changed.)
■ Clock Prescaler Settings is changed.
(INFCR:SEL[1:0]=01
430
Table 21.2-10 Common Machine Clock Frequencies is changed.
(400 kBit (Noise filter enabled) n Bit rate [kBit] →
400 kbit (Noise filter enabled, INFCR:SEL[1:0]= 01B) n Bit rate [kbit])
431 21.2.8 Noise Filter Configuration Register (INFCR) is added.
453 Figure 22.4-8 Interrupt Signal Output Timing of the Extended Serial I/O Interface is changed.
26.2 Registers of the Address Match Detection Function is changed.
545
(PADR0 to PADR5 → PADR0, PADR1, PADR3 to PADR5)
549 Figure 26.4-2 Example of Program Patch Processing is changed.
Figure 28.2-1 Block Diagram of the Entire Flash Memory is changed.
557
(AQ0 to AQ17 AQ-1 → AQ0 to AQ18)
Changes (For details, refer to main body.)
2
C Seven Bit Slave Address Mask Register
2
C Clock Control Register
is added.)
B
xxii