Output Compare Register - Fujitsu MB90390 Series Hardware Manual

CHAPTER 13 16-BIT I/O TIMER
13.4.1

Output Compare Register

These 16-bit compare registers are compared with the 16-bit free-run timer. Since the
initial register values are undefined, set appropriate value before enabling the
operation. These registers must be accessed by the word access instructions. When
the value of the register matches that of the 16-bit free-run timer, a compare signal is
generated and the output compare interrupt flag is set. If output is enabled, the output
level corresponding to the compare register is reversed.
To rewriting the compare register, within the compare interrupt routine or compare
operation is disabled. Be sure not to occur simultaneously a compare match and
writing the compare register.
■ Output Compare Register
bit 15 14
Address:
003530
H
C15 C14
003531
H
003532
H
R/W R/W R/W R/W R/W
003533
H
003534
H
003535
H
003536
H
003537
H
003538
H
003539
H
00353A
H
00353B
H
00356A
H
00356B
H
00356C
H
00356E
H
R/W : Readable and writable
204
Figure 13.4-2 Output Compare Register (OCCP)
13 12 11 10 9 8 7
C13 C12 C11 C10 C09 C08 C07
R/W R/W R/W R/W R/W R/W R/W R/W
6 5 4 3 2 1 0
C06 C05 C04 C03 C02 C01 C00
R/W R/W R/W
OCCP0
OCCP1
:
OCCP7
Initial value
X X X X X X X X X X X X X X X X
bit0 to bit7
OCCPn lower bits
C00 Compare Data Reg. 0
C01 Compare Data Reg. 1
C02 Compare Data Reg. 2
C03 Compare Data Reg. 3
C04 Compare Data Reg. 4
C05 Compare Data Reg. 5
C06 Compare Data Reg. 6
C07 Compare Data Reg. 7
n = 0, 1, 2, 3, 4, 5, 6, 7
bit8 to bit15
OCCPn upper bits
C08 Compare Data Reg. 8
C09 Compare Data Reg. 9
C10 Compare Data Reg. 10
C11 Compare Data Reg. 11
C12 Compare Data Reg. 12
C13 Compare Data Reg. 13
C14 Compare Data Reg. 14
C15 Compare Data Reg. 15
n = 0, 1, 2, 3, 4, 5, 6, 7
B