Fujitsu MB90390 Series Hardware Manual page 431

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A/D bit (serial control register (SCR2/SCR3): address/data type select bit)
The behavior of this bit is different between MB90V390H/MB90F394H(A) and MB90V390HA/
MB90V390HB/MB90394HA.
MB90V390H/MB90F394H(A):
• Special care has to be taken when using the A/D bit (Address-Data-Bit for multiprocessor mode 1) of
the Serial Control Register. This bit is both a control and a flag bit, because writing to it sets the A/D bit
for transmission, whereas reading from it returns the last received A/D bit. Internally, the received and
the transmitted value are stored in different registers, but in Read-Modify-Write instructions, the
received value is read, modified and then written back for transmission. This can lead to a wrong value
in the A/D bit, when one of the other bits in the same register is accessed by an instruction of this kind.
Therefore, this bit should be written by the last register access before transmission. Alternatively, using
byte wise access and writing the correct values for all bits at once avoids this problem.
• Furthermore, the A/D bit is not buffered like the transmission data register.
Changing the bit during transmission will alter the A/D bit of the currently transmitted data.
MB90V390HA/MB90V390HB/MB90394HA:
• This bit is both a control and a flag bit, because writing to it sets the A/D bit for transmission, whereas
reading from it returns the last received A/D bit. Internally, the received and the transmitted A/D bit
values are stored in different registers.
The A/D bit of the transmission is read when the RMW system instruction is used, and the received A/D
data is read as for other reading.
• When the TDRE bit becomes "1" from "0" when the transmission operates, the A/D bit for the
transmission is loaded into the transmission shift register with the data of the transmission data register
(TDR2/TDR3). Therefore, set the A/D bit to the A/D bit for the transmission before writing in the
transmission data register (TDR2/TDR3).
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Software reset of UART2/UART3
Perform the software reset (SMR2/SMR3:UPCL=1), when the TXE bit of the SCR2/SCR3 register is "1".
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LIN Synch field wait state
MB90V390H/MB90F394H(A): In modes 0 and 3, the LBD bit in the ESCR2/ESCR3 register is set to "1"
if the serial input is kept at "0" for more than equal to 11-bit times. When LBD is set to "1", the reception
error flags (SSR2/SSR3:FRE, SSR2/SSR3:ORE, SSR2/SSR3:PE) and the reception data register full flag
(SSR2/SSR3:RDRF) are cleared. Then the UART2, UART3 waits for the following synch field to be
received. If the UART2, UART3 is set into this state for other reasons than the synch break, it should be
initialized by the software reset (SMR2/SMR3: UPCL=1).
MB90V390HA/MB90V390HB/MB90394HA: In mode 3 (LIN operation), the LBD bit in the ESCR2/
ESCR3 register is set to "1" if the serial input is kept at "0" for more than equal to 11-bit times. Then the
UART2, UART3 waits for the following synch field to be received. If the UART2, UART3 is set into this
state for other reasons than the synch break, it should be initialized by the software reset (SMR2/
SMR3:UPCL=1).
CHAPTER 20 UART2, UART3
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