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20.4.4
Reception and Transmission Data Register
(RDR2/RDR3 and TDR2/TDR3)
The reception data register (RDR2/RDR3) holds the received data. The transmission
data register (TDR2/TDR3) holds the transmission data. Both RDR2/RDR3 and TDR2/
TDR3 registers are located at the same address.
■ Bit Configuration of Reception and Transmission Data Registers (RDR2/RDR3 and
TDR2/TDR3)
Figure 20.4-5 Transmission and Reception Data Registers (RDR2/RDR3 and TDR2/TDR3)
Address:
RDR3/TDR3: 00351A
RDR2/TDR2: 0035DA
■ Reception Data Register (RDR2/RDR3)
RDR2/RDR3 is the register that contains reception data. The serial data signal transmitted to the SIN2/
SIN3 pin is converted in the shift register and stored there. When the data length is 7 bits, the uppermost bit
(D7) contains "0". When reception is complete the data is stored in this register and the reception data full
flag bit (SSR2/SSR3: RDRF) is set to "1". If a reception interrupt request is enabled at this point, a
reception interrupt occurs.
Read RDR2/RDR3 when the RDRF bit of the status register (SSR2/SSR3) is "1". The RDRF bit is cleared
automatically to "0" when RDR2/RDR3 is read. Also the reception interrupt is cleared if it is enabled and no
error has occurred. For MB90V390H/MB90F394H(A), the RDRF bit is also cleared when a LIN break is
detected (LBD=1).
Data in RDR2/RDR3 is invalid when a reception error occurs (SSR2/SSR3: PE, ORE, or FRE = 1).
bit
7
6
5
4
3
H
H
R/W R/W R/W R/W
R/W
R/W: Readable and writable
2
1
0
Initial value
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
R/W
R/W R/W
bit 7 to 0
R/W
Read
Read from Reception Data Register
Write
Write to T r ansmission Data Register
CHAPTER 20 UART2, UART3
[RDR2/RDR3]
B
[TDR2/TDR3]
B
Data Registers
357
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