Fujitsu MB90390 Series Hardware Manual page 138

CHAPTER 6 CLOCK MODULATOR
■ Clock Modulator Control Register Contents
Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (1/3)
Bit name
PMOD:
bit7 Phase modulation
enable bit
bit6, bit5 Reserved
bit4 Reserved
bit3 Undefined
110
Writing "0": Phase modulation disabled (default).
Writing "1": Modulator enabled in phase modulation mode, MCU is running with phase
modulated clock
• To enable the modulator in phase modulation mode, PMOD must be set to "1".
For phase modulation mode, the modulator must remain in power down mode. I.e.
PDX must be set to "0".
• Before the modulator can be enabled, the PLL must deliver a stable reference clock
(PLL lock time must be elapsed - refer to the CLOCK chapter in the hardware
manual).
• The specified PLL frequency range for phase modulation mode is 15MHz to
25MHz.
• Whenever the PLL output frequency is changed or the PLL is switched OFF e.g. in
power down modes, the modulator must be disabled before → PMOD=0 and 4 NOP
cycles must follow the PMOD-bit access.
• After enabling the phase modulation mode, the clock switches immediately to
modulated clock without glitches in the clock signal.
Please refer to the application note for a description of the recommended startup
sequence.
• The modulator must not be set to phase modulation and frequency modulation mode
at the same time (PMOD=1 and FMOD=1, PDX=1). Before the modulator can be
enabled in phase modulation mode (PMOD=1), the FMOD, FMODRUN and PDX
bit must be "0".
• The FMODRUN status flag is "0" if the modulator is enabled in phase modulation
mode.
The status of the clock signal is indicated by PMOD. PMOD=1 clock is phase
modulated.
• The pulse width of the phase modulated clock signal can vary ± 1.2 ns.
E.g. at F0 = 20 MHz unmodulated input clock, T0 = 50ns. Tmodmin = 50ns - 1.2 ns
= 48.8 ns → Fmodmax = 1/48.8 ns = 20.49 MHz.
Always write "0" to these bits.
Always write "1" to this bit.
Function
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