Fujitsu MB90390 Series Hardware Manual page 333

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Coding example
BAPL EQU
BAPM EQU
BAPH EQU
ISCS EQU
IOAL EQU
IOAH EQU
DCTL EQU
DCTH EQU
DDR6 EQU
ADER0 EQU
ICR10 EQU
ADCS0 EQU
ADCS1 EQU
ADCR0 EQU
ADCR1 EQU
TMCSR1L EQU
TMCSR1H EQU
TMRL1L EQU
TMRL1H EQU
;-----Main program---------------------------------------------------------------
CODE
START:
AND
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVW
MOV
MOV
MOV
MOV
OR
000100H ;Lower buffer address pointer
000101H ;Middle buffer address pointer
000102H ;Upper buffer address pointer
2
000103H ;EI OS status register
000104H ;Lower I/O address register
000105H ;Upper I/O address register
000106H ;Lower data counter
000107H ;Upper data counter
000016H ;Port 6 direction register
00000CH ;Analog input enable register
0000BAH ;Interrupt control register for A/D Converter
000034H ;A/D control status register
000035H ;
000036H ;A/D data register
000037H ;
000068H ;Lower control status register 1
000069H ;
003902H ;16-bit reload register 1
003903H ;
CSEG
;Assumes that the stack pointer (SP) has already
;been initialized.
CCR,#0BFH ;Disables interrupts.
ICR10,#08H ;Interrupt level: 0 (highest priority).Enables EI
;interrupt
BAPL,#00H ;Sets the address to which the conversion data is stored.
BAPM,#06H ;(Uses 600
BAPH,#00H ;
ISCS,#18H ;Transfers word data, adds 1 to the address, then
;transfers from I/O to memory.
IOAL,#36H ;Sets the address of the analog data register as the
IOAH,#00H ;transfer source address pointer.
DCTL,#06H ;Six transfer by EI
;channels.)
DDR6,#00000000B ;Sets P60 to P67 as input.
ADER0,#00111000B ;Sets P63/AN3 to P65/AN5 as analog input.
DCTH,#00H ;
ADCS0,#9DH ;Continuous conversion mode. Converts AN3 to AN5.
ADCS1,#0A8H ;Activates the 16-bit timer, starts A/D conversion, and
;enables interrupts.
TMRL1L,#0320H ;Sets the timer value to 800(320
TMCSR1H,#00H ;Sets the clock source to 125 ns and disables
;external trigger.
TMCSR1L,#12H ;Disables timer output, disables interrupts, and
;enables reload.
TMCSR1L,#13H ;Activates the 16-bit timer.
ILM,#07H ;Sets ILM in PS to level 7.
CCR,#40H ;Enables interrupts.
CHAPTER 18 8/10-BIT A/D CONVERTER
to 60B .)
H H
2
OS (two transfers each for three
2
OS when
),100 s.
H
305