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CHAPTER 19 UART0, UART1
19.9.3
Flag Set Timings for a Transmit Operation
TDRE is set and an interrupt request to the CPU is generated when the data written in
UODR register is transferred to the internal shift register and the next data can be
written to UODR.
■ Flag Set Timings for a Transmit Operation
UODR write
TDRE
T r ansmit interrupt
SOT0 output
332
Figure 19.9-6 TDRE Set Timing (Mode 0)
Interrupt request to the CPU
ST D0 D1
ST: Start bit
D0 to D7: Data bits
D2 D3 D4
D5 D6 D7
SP: Stop bit
SP SP ST D0 D1
D2 D3
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