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23.6.8
Transmission Request Register (TREQR)
Transmission request register (TREQR) stores transmission requests to the message
buffers (x) or displays their state.
■ Transmission Request Register (TREQR)
Figure 23.6-11 Configuration of the Transmission Request Register (TREQR)
Address:
CAN0: 000073
CAN1: 000083
CAN2: 003573
CAN3: 003583
CAN4: 003593
Address:
CAN0: 000072
CAN1: 000082
CAN2: 003572
CAN3: 003582
CAN4: 003592
[bit15 to bit0] TREQ15 to TREQ0:
When "1" is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the remote
frame receiving wait register (RFWTR)
transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving
register (RRTRR)
is already "1" when "1" is written to TREQx.
*1: For RFWTR and TRTRR, see Sections "23.6.9 Transmission RTR Register (TRTRR)" and "23.6.10
Remote Frame Receiving Wait Register (RFWTR)".
*2: For cancellation of transmission, see Sections "23.6.11 Transmission Cancel Register (TCANR)" and
"23.6.12 Transmission Complete Register (TCR)".
Writing "0" to TREQx is ignored.
"0" is read when a Read Modify Write (RMW) instruction is performed.
If clearing (to "0") at completion of the transmit operation and setting by writing "1" are concurrent,
clearing is preferred.
If "1" is written to more than one bit, transmission is performed, starting with the lower-numbered message
buffer (x).
TREQx is "1" while transmission is pending, and becomes "0" when transmission is completed or canceled.
bit
15
14
13
12
11
H
TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8
H
H
R/W R/W R/W R/W
R/W
H
H
7
6
5
4
3
bit
H
TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0
H
H
R/W R/W R/W R/W
R/W
H
H
*1
is "0", transmission starts immediately. However, if RFWTx = 1,
*1
becomes "1"). Transmission starts
CHAPTER 23 CAN CONTROLLER
10
9
8
TREQRn (upper)
Initial value
0 0 0 0 0 0 0 0
R/W
R/W R/W
2
1
0
TREQRn (lower)
Initial value
0 0 0 0 0 0 0 0
R/W
R/W R/W
*2
immediately even when RFWTx = 1, if RRTRx
B
B
n = 0, 1, 2, 3, 4
481
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