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CHAPTER 21 400 kHz I
- Condition 2 in which an interrupt (INT bit = 1) upon detection of " AL bit = 1 " does not occurs
When an instruction which generates a start condition by enabling I
executed (setting the MSS bit in the IBCR register to "1") with the I
master.
This is because, as shown in Figure 21.2-4, when the other master on the I
communication with I
condition detected (BB bit = 0).
Figure 21.2-4 Diagram of Timing at which an Interrupt Upon Detection of " AL Bit = 1 " does not Occur
SCL pin
SDA pin
EN bit
MSS bit
AL bit
BB bit
INT bit
If a symptom as described above can occur, follow the procedure below for software
processing.
1) Execute the instruction that generates a start condition (set the MSS bit to "1").
2) Use, for example, the timer function to wait for the time × for three-bit data transmission at
the I
Example: Time for three-bit data transmission at an I
3) Check the AL and BB bits in the IBSR register and, if the AL and BB bits are "1" and "0",
respectively, set the EN bit in the ICCR register to "0" to initialize I
bits are not so, perform normal processing.
420
2
C INTERFACE
2
C disabled (EN bit = 0), the I
Start Condition
SLAVE ADDRESS
2
C transfer frequency set in the ICCR register.
{1/(100 × 10
)} × 3 = 30 μs
3
2
C bus enters the occupied state with no start
INT bit interruption is not generated
in 9th clock.
ACK
DAT
2
C operation (EN bit = 1) is
2
C bus occupied by another
Stop Condition
ACK
0
0
2
C transfer frequency of 100 kHz
2
C. When the AL and BB
2
C bus starts
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