Table of Contents
Advertisement
CHAPTER 22 SERIAL I/O
■ Bit Functions of Serial Mode Control Status Register (SMCS)
Table 22.2-1 Bit Functions of Serial Mode Control Status Register
Bit name
SMD2 to SMD0:
bit15 to
Shift clock mode
bit13
selection bits
SIE:
bit12
Serial I/O interrupt
enable bit
SIR:
bit11
Serial I/O interrupt
request bit
BUSY:
bit10
Transfer status bit
STOP:
bit9
Stop bit
STRT:
bit8
Start bit
MODE:
bit3
Serial mode selection
bit
BDS:
bit2
Bit direction select
bit
SOE:
bit1
Serial output enable
bit
SCOE:
bit0
Shift clock output
enable bit
442
Shift Clock Mode selection bits, see Table 22.2-2.
Serial I/O interrupt enable bit.
This bit controls the serial I/O interrupt request as shown Figure 22.2-1. This bit is initialized to "0"
upon a reset. This bit is readable and writable.
Serial I/O interrupt request bit.
When serial data transfer is completed, "1" is set to this bit. If this bit is set while interrupts are
enabled (SIE=1), an interrupt request is issued to the CPU. The clear condition varies with the
MODE bit.
When "0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is written to
the MODE bit, the SIR bit is cleared by reading or writing to SDR. When the system is reset or "1"
is written to the STOP bit, the SIR bit is cleared regardless of the MODE bit value.
Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a read-modify-
write (RMW) instruction.
Transfer status bit.
The transfer status bit indicates whether serial transfer is being executed. This bit is initialized to "0"
upon a reset. This is a read-only bit.
Stop bit.
The stop bit forcibly terminates serial transfer. When "1" is written to this bit, the transfer is stopped.
This bit is initialized to "1" upon a reset. This bit is readable and writable.
Start bit.
The start bit activates serial transfer. Writing "1" to this bit starts the data transfer when the MODE
bit is set to "0". When the MODE bit is set to "1" and the STRT bit is set to "1", writing the data into
serial data register starts the transfer.
Writing "1" is ignored while the system is performing serial transfer or standing by for a serial shift
register read or write. Writing "0" has no effect. "0" is always read.
Serial mode selection bit.
The serial mode selection bit is used to select the conditions to start the transfer operation from the
stop state. This bit must not be updated during operation.
This bit is initialized to "0" upon a reset and can be read or written to. To activate the intelligent I/O
service, ensure that "1" is written to this bit.
Bit Direction Select bit.
When serial data is input or output, this bit determines from which bit data is to be transferred first,
the least significant bit (LSB first) or the most significant bit (MSB first), as shown Table 22.2-2.
Specify the bit ordering before any data is written to SDR.
Serial Output Enable bit.
This bit controls the output from the serial I/O output external pins (SOT4).
This bit is initialized to "0" upon a reset. This bit is readable and writable.
Shift clock output enable bit.
This bit controls the output from the shift clock I/O output external pins (SCK4) as shown Table 22.2-2.
Ensure that "0" is written to this bit when data is transferred for each instruction in external shift
clock mode.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
Function
Advertisement
Table of Contents
