Fujitsu MB90390 Series Hardware Manual page 373

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Oversampling Unit
The oversampling unit oversamples the incoming data at the SIN2/SIN3 pin for five times with the
machine clock. It is not operated in synchronous operation mode.
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Interrupt Generation Circuit
The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a
corresponding enable flag is set and an interrupt case occurs the interrupt will be generated immediately.
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LIN synch Break and Synchronization Field Detection Circuit
The LIN break and LIN synchronization field detection circuit detects a LIN break, if a LIN master node is
sending a message header. If a LIN break is detected a special flag bit is generated. The first and the fifth
falling edge of the LIN synchronization field is recognized by this circuit by generating an internal signal
(LSYN) for the Input Capture Unit to measure the actual serial clock time of the transmitting master node.
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LIN Synch Break Generation Circuit
The LIN break generation circuit generates a LIN break of a determined length.
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Bus Idle Detection circuit
The bus idle detection circuit recognizes if neither reception nor transmission is going on. In this case, the
circuit generates the special flag bits TBI and RBI.
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LIN-UART2, LIN-UART3 Serial Mode Register (SMR2/SMR3)
This register performs the following operations:
• Selecting the LIN-UART2, LIN-UART3 operation mode
• Selecting a clock input source
• Selecting if an external clock is connected "one-to-one" or connected to the reload counter
• Resetting dedicated reload timer
• Resetting the LIN-UART2, LIN-UART3 (preserving the settings of the registers)
• Specifying whether to enable serial data output to the corresponding pin
• Specifying whether to enable clock output to the corresponding pin
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Serial Control Register (SCR2/SCR3)
This register performs the following operations:
• Specifying whether to provide parity bits
• Selecting parity bits
• Specifying a stop bit length
• Specifying a data length
• Selecting a frame data format in mode 1
• Clearing the error flags
• Specifying whether to enable transmission
• Specifying whether to enable reception
CHAPTER 20 UART2, UART3
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