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CHAPTER 3 INTERRUPTS
3.5.3
Multiple interrupts
As a special case, no hardware interrupt request can be accepted while data is being
written to the I/O area. For MB90390 Series, this includes the address ranges "00
"BF
", ("3100
" to "31FF
H
H
"37FF
", "3900
" to "39FF
H
H
"3FFF
". This is intended to prevent the CPU from operating falsely because of an
H
interrupt request issued while an interrupt control register for a resource is being
updated. If an interrupt occurs during interrupt processing, a higher-level interrupt is
processed first.
■ Multiple Interrupts
2
The F
MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another
interrupt is being processed, control is transferred to the high-level interrupt after the currently executing
instruction is completed. After processing of the high-level interrupt is completed, the original interrupt
processing is resumed. An interrupt of the same or lower level may be generated while another interrupt is
being processed. If this happens, the new interrupt request is suspended until the current interrupt
processing is completed, unless the ILM value or I flag is changed by an instruction.
The extended intelligent I/O service cannot be activated from multiple sources; while an extended
intelligent I/O service is being processed, all other interrupt requests or extended intelligent I/O service
requests are suspended.
Figure 3.5-2 shows the order of the registers saved in the stack.
MSB
"H"
"L"
68
", "3300
" to "33FF
H
H
", "3B00
H
H
Figure 3.5-2 Registers Saved in Stack
Word (16 bits)
AH
AL
DPR
DTB
PC
PS
",) "3500
H
H
" to "3BFF
", "3D00
H
LSB
ADB
PCB
" to "35FF
", "3700
H
" to "3DFF
" and "3F00
H
H
SSP (SSP value before interrupt)
SSP (SSP value after interrupt)
" to
H
" to
H
" to
H
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