Block Diagram Of The Clock Generation Block - Fujitsu MB90390 Series Hardware Manual

5.2

Block Diagram of the Clock Generation Block

The clock generation block consists of five blocks:
• System clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait time selector
■ Block Diagram of the Clock Generation Block
Figure 5.2-1 shows a block diagram of the clock generation block.
Pin
RST
Interrupt
clearing
Clock
CS2
Selector
Bit8 of PLL and
Special Configuration
Control Register
(PSCCR) : bit8
Pin
X0
Pin
X1
System clock
generation circuit
Figure 5.2-1 Block Diagram of the Clock Generation Block
Low-Power Consumption Mode Control Register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
Machine clock
-
PLL multiplier circuit
Clock Selection register (CKSCR)
Mainclock
Divide- Divide-
by-2 by-1024
HCLK
Time-base Timer
-
Interm.
cycle sel.
CPU intermittent
operation
selector
Standby
control
circuit
Oscillation stabilization wait clear
2
-
MCM WS1 WS0 MCS CS1 CS0
Divide- Divide-
by-2 by-4
Watchdog Timer
Note: The Clock Modulator is not shown in this diagram, please refer to
chapter 6 for details.
CHAPTER 5 CLOCKS
Pin high-
Pin high-
impedance
impedance
control circuit
control
Internal reset
Internal
generation
reset
circuit
CPU clock
CPU
control
clock
circuit
Stop and
sleep signals
Stop signal
Peripheral
Peripheral
clock control
clock
circuit
Oscillation
stabilization
wait time
interval selector
2
Divide- Divide- Divide-
by-4 by-4 by-2
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