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Table 20.4-3 Functions of Each Bit of Status Register (SSR2/SSR3) (1/2)
Bit name
PE:
bit15
Parity error flag
bit
ORE:
bit14
Overrun error
flag bit
FRE:
bit13
Framing error
flag bit
RDRF:
bit12
Receive data full
flag bit
TDRE:
Transmission
bit11
data empty flag
bit
BDS:
Transfer
bit10
direction
selection bit
• This bit is set to "1" when a parity error occurs during reception at PEN=1 and is cleared
when "1" is written to the CRE bit of the serial mode register (SMR2/SMR3).
MB90V390H/MB90F394H(A): This bit is also cleared when a LIN break is detected
(LBD=1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the reception data register (RDR2/RDR3) is invalid when this flag is set.
• This bit is set to "1" when an overrun error occurs during reception and is cleared when
"0" is written to the CRE bit of the serial mode register (SMR2/SMR3).
MB90V390H/MB90F394H(A): This bit is also cleared when a LIN break is detected
(LBD=1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the reception data register (RDR2/RDR3) is invalid when this flag is set.
• This bit is set to "1" when a framing error occurs during reception and is cleared when
"0" is written to the CRE bit of the serial mode register 1 (SMR2/SMR3).
MB90V390H/MB90F394H(A): This bit is also cleared when a LIN break is detected
(LBD=1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the reception data register (RDR2/RDR3) is invalid when this flag is set.
Note:
When framing error is detected by the first or the second bit of the stop bit at SBL=1,
this bit is set to "1" as for either stop bit.
Thus, it is necessary to determine whether the receive data is enabled by the second bit
of the stop bit.
• This flag indicates the status of the reception data register (RDR2/RDR3).
• This bit is set to "1" when reception data is loaded into RDR2/RDR3 and can only be
cleared to "0" when the reception data register (RDR2/RDR3) is read.
MB90V390H/MB90F394H(A): This bit is also cleared when a LIN break is detected
(LBD=1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• This flag indicates the status of the transmission data register (TDR2/TDR3).
• This bit is cleared to "0" when transmission data is written to TDR2/TDR3 and is set to
"1" when data is loaded into the transmission shift register and transmission starts.
• A transmission interrupt request is generated if both this bit and the TIE bit are "1".
• If the LBR bit in the ECCR2/ECCR3 register is set to "1" while the TDRE bit is "1",
then this bit once changes to "0". When effective data to TDR2/TDR3 doesn't exist after
the completion of LIN synch break generator, the TDRE bit returns to "1".
Note:
This bit is set to "1" (TDR2/TDR3 empty) as its initial value.
• This bit selects whether to transfer serial data from the least significant bit (LSB first,
BDS=0) or the most significant bit (MSB first, BDS=1).
This bit is fixed to "0" at mode 3.
Note:
When the BDS bit is rewritten after the receive data writing to receive data register
(RDR2/RDR3) because an upper side and lower side are replaced at the time of writing
receive data to the receive data register (RDR2/RDR3), the data of RDR2/RDR3
becomes invalid.
CHAPTER 20 UART2, UART3
Function
355
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