Rate And Data Register (Urd) - Fujitsu MB90390 Series Hardware Manual

CHAPTER 19 UART0, UART1
19.3.4

Rate and Data Register (URD)

URD selects the data transfer speed (baud rate) for UART0, UART1. The register also
holds the most significant bit (bit8) of the data when the transmit data length is 9 bits.
Set the baud rate and parity when UART0, UART1 is halted.
■ Rate and Data Register (URD)
Figure 19.3-4 Configuration of the Rate and Data Register (URD)
Address:
bit 15
ch.0 000023
H
ch.1 000027
H
R/W R/W R/W R/W
R/W : Readable and writable
: Initial value
320
14 13 12 11 10 9
R/W R/W R/W R/W
8
URD0 URD1
Initial value
0 0 0 0 0 0 0 X
B
bit8
D8 UIDRn/UODRn Data bit 8
X read/write
bit9
P
0 Even parity
1 Odd parity
bit10
BCH0 Baud Rate Clock Change 1
- see description for details
bit14 to bit11
RC3 to RC0
- see description for details
bit15
BCH Baud Rate Cloc
- see description for details
Parity bit
Rate Control