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Reference: Main changes (Rev.2 → Rev.3)
Page
Table 13.5-3 Input Capture Edge Register Bits (Upper and Lower)
Bit name of bit10 is changed.
220
(IUCE → IUCE1/IUCE5)
bit2 is changed.
Figure 14.5-1 Output Pin Function of 16-bit Reload Timer (1) is changed.
234
Figure 14.5-2 Output Pin Function of 16-bit Reload Timer (2) is changed.
235
Figure 14.6-1 Counter State Transitions is changed.
Figure 15.2-1 Watch Timer Registers
WTCR is changed.
(0 0 0 - - 0 0 0 → 000XX000)
WTSR is changed.
(- - - X X X X X → XXXXXXXX)
WTBR1 is changed.
(- - X X X X X X → XXXXXXXX)
239
WTHR is changed.
(- - - X X X X X → XXXXXXXX)
WTMR is changed.
(- - X X X X X X → XXXXXXXX)
Notes is changed.
(timer control register (WTC) → timer control register (WTCR))
243
Table 15.2-2 Timer Control Register (Upper) is changed.
Figure 15.2-5 Configuration of the Second/Minute/Hour Registers is changed.
245
(00354C
H
Figure 16.2-1 8/16-bit PPG ch.0 Block Diagram is changed.
(PRLBH0 → PRLL0)
250
((Temporary buffer) is added.)
Figure 16.2-2 8/16-bit PPG ch.1 Block Diagram is changed.
(PRLBH1 → PRLL1)
251
((Temporary buffer) is added.)
● Details of pins in block diagram is added.
● PPG operation mode control register 0 (PPGC0) is added.
● PPG0/1 count clock select register (PPG01) is added.
● PPG0 reload registers (PRLH0 and PRLL0) is added.
● PPG0 down counter (PCNT0) is added.
252, 253
● PPG0 temporary buffer (PRLBH0) is added.
● Reload register L/H selector is added.
● Count clock selector is added.
● PPG output control circuit is added.
■ 8/16-bit PPG Registers
PPGCn is changed.
((0)(-)(0)(0)(0)(-)(-)(1) → (0)(X)(0)(0)(0)(X)(X)(1))
254
PPGCm is changed.
((0)(-)(0)(0)(0)(0)(0)(1) → (0)(X)(0)(0)(0)(0)(0)(1))
PPGnm is changed.
((0)(0)(0)(0)(0)(0)(-)(-) → (0)(0)(0)(0)(0)(0)(X)(X))
Figure 16.3-3 Configuration of the PPG0/1 Clock Select Register (PPG01)
259
PCM1 and PCS1 in "Clock input from time-base timer" are changed.
(0 → 1)
Changes (For details, refer to main body.)
is deleted.)
xvii
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