Fujitsu MB90390 Series Hardware Manual page 424

CHAPTER 20 UART2, UART3
●
Inter-CPU connection
As shown in Figure 20.7-14, a communication system consists of one master CPU and multiple slave CPUs
connected to two communication lines. UART2, UART3 can be used for the master or slave CPU.
Figure 20.7-14 Connection Example of UART2, UART3 Master/Slave Communication
Master CPU
●
Function selection
Select the operation mode and data transfer mode for master/slave communication as shown in Table 20.7-
3.
Table 20.7-3 Selection of the Master/Slave Communication Function
Master CPU
Address
transmission
and
Mode 1
reception
(transmit/receive
Data
A/D-bit)
transmission
and
reception
Communication procedure
When the master CPU transmits address data, communication starts. The A/D bit in the address data is
set to "1", and the communication destination slave CPU is selected. Each slave CPU checks the
address data using a program. When the address data indicates the address assigned to a slave CPU, the
slave CPU communicates with the master CPU.
Figure 20.7-15 shows a flowchart of master/slave communication (multiprocessor mode).
396
SOT1
SIN1
SOT SIN
Slave CPU #0
Operation mode
Slave CPU
Mode 1
(transmit/receive
A/D-bit)
SOT
Slave CPU #1
Data Parity
A/D= 1 + 7-
bits or 8-bits
address
None
A/D= 0 + 7-
bits or 8-bits
data
SIN
Synchronization Stop
method bit
1bit or
Asynchronous
2 bits
Bit
direction
LSB first
or
MSB first