Delayed Interrupt Operation - Fujitsu MB90390 Series Hardware Manual

CHAPTER 4 DELAYED INTERRUPT
4.3

Delayed Interrupt Operation

When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the
delayed interrupt source module is set and an interrupt request is issued to the
interrupt controller.
■ Delayed Interrupt Occurrence
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the delayed interrupt
source module is set and an interrupt request is issued to the interrupt controller. If this interrupt has the
highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to
2
the F MC-16LX CPU. The F
interrupt request, and starts the hardware interrupt processing microprogram as soon as the current
instruction is completed if the interrupt level of the request is higher than that of the ILM bit. The interrupt
processing routine for this interrupt is thus executed.
Delayed interrupt source moduleInterrupt controller
DIRR
84
2
MC-16LX CPU compares the ILM bit of its internal CCR register and the
Figure 4.3-1 Delayed Interrupt Issuance
WRITE
Other requests
ICR
ICR
yy
CMP
xx
2
F MC-16LX CPU
IL
CMP
ILM
INTA