Extended Status/Control Register (Escr2/Escr3) - Fujitsu MB90390 Series Hardware Manual

20.4.5

Extended Status/Control Register (ESCR2/ESCR3)

The extended status control register (ESCR2/ESCR3) provides several functions, such
as LIN synch break interrupt enabling/disabling, LIN synch break length selection, LIN
synch break detection, direct access to the SIN2/SIN3 and SOT2/SOT3 pins, continuous
clock output in UART2, UART3 synchronous clock mode, and sampling clock edge
setting.
■ Extended Status/Control Register (ESCR2/ESCR3)
Figure 20.4-6 shows the bit configuration of the extended status control registers (ESCR2/ESCR3), and
Table 20.4-4 shows the functions of each bit in the resisters.
Figure 20.4-6 Configuration of the Extended Status/Control Register (ESCR2/ESCR3)
Address:
ESCR3: 00351D
H
ESCR2: 0035DD
R/W : Readable and writable
X : Undefined value
: Initial value
* : See Table 20.4-4 for RMW access.
15 14 13 12 11 10
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
H
R/W R/W R/W R/W R/W R/W
Initial value
9 8
0 0 0 0 0 X 0 0
R/W R/W
bit8
SCES Sampling Clock Edge Selection (Mode 2)
0 Sampling on rising clock edge (normal)
1 Sampling on falling clock edge (inverted clock)
bit9
CCO
0 Continuous Clock Output disabled
1 Continuous Clock Output enabled
bit10
SIOP
write (if SOPE = 1 )
0 SOT is forced to "0"
1 SOT is forced to "1"
bit11
SOPE Enable Serial Output pin direct Access
0 Serial Output pin direct access disable
1 Serial Output pin direct access enable
bit13 bit12
LBL1 LBL0
0 0
0 1
1 0
1 1
bit14
LBD
0 Clear LIN synch break
detected flag
1 Ignored
bit15
LBIE LIN synch break detection Interrupt enable
0 LIN synch break interrupt disable
1 LIN synch break interrupt enable
CHAPTER 20 UART2, UART3
B
Continuous Clock Output (Mode 2)
Serial Input / Output Pin Access
read
reading the actual value of
SIN
LIN synch break length select
LIN break length 13 bit times
LIN break length 14 bit times
LIN break length 15 bit times
LIN break length 16 bit times
LIN synch break detected flag
*
write read
No LIN synch break detected
LIN synch break detected
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