Fujitsu MB90390 Series Hardware Manual page 349

■ Rate and Data Register (URD) Contents
Table 19.3-3 Function of Each Bit of the Rate and Data Register
Bit name
BCH, BCH0:
bit15,
Baud rate clock
bit10
change bits
bit14 to RC3, RC2, RC1,
bit11 RC0
P:
bit9
Parity bit
D8:
bit8 UIDRn/UODRn
data bit 8
Specifies the machine cycles for the baud rate clock (see Section "19.4 UART0,
UART1 Operation" for details).
Divider
BCH BCH0
ratio
0 0
0 1
1 0
1 1
Selects the clock input for the UART0, UART1 port (see Section "19.4 UART0,
UART1 Operation" for details).
RC3 to
RC0
0000
B
Dedicated baud rate generator
to
1011
B
1101 16-bit Reload Timer 0
B
1111
External Clock
B
Sets even or odd parity when parity is active (PEN = 1).
"0": Even parity
"1": Odd parity
Holds the bit8 of the transfer data in mode 2 or 3 (9-bit data length) and no parity.
Treated as bit8 of the UIDR register for reading. Treated as bit8 of the UODR register
for writing. The bit has no meaning in the other modes. Write to D8 only when TDRE = 1
in the USR register.
Function
Setting example for different Machine Cycles
6 For 24 MHz: 24/6 = 4 MHz
For 16 MHz: 16/4 = 4 MHz
4
For 12 MHz: 12/3 = 4 MHz
3
For 20 MHz: 20/5 = 4 MHz;
5
10 MHz: 10/5 = 2 MHz
For
Clock Input
CHAPTER 19 UART0, UART1
321