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CHAPTER 3 INTERRUPTS
Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels
IL2
[bit11, bit3] ISE (extended intelligent I/O service enable bits)
The ISE bit is readable and writable. In response to an interrupt request, EI
set in the ISE bit and an interrupt sequence is activated when "0" is set in the ISE bit. Upon completion
of EI
function, the ISE bit must be set to "0" on the software side.
Upon a reset, the ISE bit is initialized to "0".
[bit15 to bit12, bit7 to bit4] ICS3 to ICS0 (extended intelligent I/O service channel select bits)
ICS3 to ICS0 are write-only bits. These bits specify the EI
determine the intelligent I/O service descriptor addresses in memory, which is explained later. The ICS
bits are initialized by a reset.
Table 3.3-2 lists ICS bits, channel numbers, and descriptor addresses.
60
IL1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
2
OS, the ISE bit is cleared to a zero. If the corresponding peripheral does not have the EI
IL0
0
0 (Strongest)
1
1
0
2
1
3
0
4
1
5
0
6 (Weakest)
1
7 (No interrupt)
2
OS channel. The values set in these bits
Level
2
OS is activated when "1" is
2
OS
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