Serial Mode Control Status Register (Smcs) - Fujitsu MB90390 Series Hardware Manual

CHAPTER 22 SERIAL I/O
22.2.1

Serial Mode Control Status Register (SMCS)

The serial mode control status register (SMCS) controls the serial I/O transfer mode.
■ Upper Byte of Serial Mode Control Status Register (SMCS)
Figure 22.2-1 Configuration of the Serial Mode Control Status Register (Upper Byte)
Address
00002D
H
R/W : Readable and writable
: Read only
R
: Initial value
440
bit15 bit14 bit13 bit12
SMD2 SMD1 SMD0 SIE
R/W R/W R/W R/W
bit11 bit10 bit9 bit8
SIR BUSY STOP STRT
R/W R R/W R/W
STRT
0 Writing "0" has no effect. "0" is always read
1 Writing "1" activates serial transfer, if MODE = 0
STOP
0 Normal operation
1 Transfer stopped
BUSY
Transfer is stopped or standing by for serial data
0
register Read/Write
1 Serial transfer is active
SIR Serial I/O Interrupt Request bit
0 No interrupt is requested
1 If SIE = 1, an interrupt request is issued to CPU
SIE Serial I/O Interrupt Enable bit
0 Serial I/O interrupt disabled
1 Serial I/O interrupt enabled
SMD2 to
Shift Clock Mode selection bits
SMD0
000 Prescaler output clock is divided by 2
B
001 Prescaler output clock is divided by 4
B
010 Prescaler output clock is divided by 16
B
011 Prescaler output clock is divided by 32
B
100 Prescaler output clock is divided by 64
B
101 External shift clock mode
B
110 Prescaler output clock is divided by 8
B
111 Prescaler output clock is divided by 128
B
Initial value
00000010
Start bit
Stop bit
Transfer Status bit
B