Table of Contents
Advertisement
17.3
Operations of DTP/External Interrupts
When the interrupt flag is set, this block signals an interrupt to the interrupt controller.
The interrupt controller judges the priority levels of the simultaneous interrupts, and
issues an interrupt request to the F
the highest priority. The F
register and the interrupt request. If the interrupt level of the request is higher than that
indicated by the ILM bits, the F
processing microprogram as soon as the currently executing instruction is terminated.
■ External Interrupt Operation
In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from the
interrupt controller, identifies that the request is for interrupt processing based on that information, and
branches to the interrupt processing microprogram. The interrupt processing microprogram reads the
interrupt vector area and issues an interrupt acknowledgment signal for the interrupt controller. Then, the
microprogram transfers the jump destination address of the macro instruction generated from the vector to
the program counter, and executes the user interrupt processing program.
External interrupt/DTP
Cause
2
MC-16LX CPU if the interrupt from this block has
2
MC-16LX CPU compares the ILM bits of its internal CCR
2
MC-16LX CPU activates the hardware interrupt
Figure 17.3-1 External Interrupt
Other request
ELVR
EIRR
ENIR
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
Interrupt controller
ICR
yy
CMP
ICR
xx
2
F
MC-16LX CPU
IL
CMP
ILM
INTA
273
Advertisement
Table of Contents
