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21.2.8
Noise Filter Configuration Register (INFCR)
The Noise Filter Configuration Register (INFCR) is used to configure the filter time of
the SDA and SCL noise filters as a function of the machine clock frequency.
It is only available in MB90394HA, MB90V390HA and MB90V390HB.
■ Noise Filter Configuration Register (INFCR)
R/W :Readable and writable
-
: Undefined
■ Noise Filter Configuration Register Contents
Table 21.2-11 Function of Each Bit of the Noise Filter Configuration Register
Bit name
bit15 to bit10
Undefined
bit9, bit8
SEL1, SEL0
15
14
13
12
-
-
-
-
0035A9
H
-
-
-
-
These bits return "X" during reading. Always write "0" to these bits
MB90394HA, MB90V390HA, MB90V390HB:
These bits select the filter time of noise filters built into the SDA and SCL I/O pads.
The noise filter will suppress single spikes with a pulse width between 0 ns (minimum)
and a maximum value according to the table below. The maximum depends on the
phase relationship between I
SEL1
SEL0
0
0
0
1
1
0
1
1
CHAPTER 21 400 kHz I
11
10
9
8
INFCR
-
-
SEL1 SEL0
Initial value
X X X X X X 0 1
-
-
R/W R/W
Function
2
C signals (SDA, SCL) and machine clock.
maximum length of suppressed spikes
0.5 to 1 machine clock cycles
1 to 1.5 machine clock cycles (initial value)
1.5 to 2 machine clock cycles
2 to 2.5 machine clock cycles
2
C INTERFACE
B
431
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