Fujitsu MB90390 Series Hardware Manual page 414

CHAPTER 20 UART2, UART3
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Clock supply
In clock synchronous mode (normal), the number of clock cycles for the clock signal must be the same as
the number of transmission and reception bits for the data including start and stop bits. If the MS bit of the
ECCR2/ECCR3 register is "0" (master mode) and the SCKE bit of the SMR2/SMR3 register is "1" (serial
clock output enabled), the consistent clock cycles are generated automatically. If the MS bit of the ECCR2/
ECCR3 register is "1" (slave mode), or if serial clock output is disabled (SMR2/SMR3: SCKE = 0), clocks
equivalent to each block of bits of transmit/receive data are required to be externally provided. While there
is no communication, the clock signal must be kept at "H" as the mark level.
If the SCDE bit of the ECCR2/ECCR3 register is "1", the clock output signal is delayed. The amount of
this delay is different between MB90V390H/MB90F394H(A) and MB90V390HA/MB90V390HB/
MB90394HA.
MB90V390H/MB90F394H(A): If the SCDE bit of the ECCR2/ECCR3 register is "1", the clock output
signal is delayed by one machine clock cycle.
MB90V390HA/MB90V390HB/MB90394HA: If the SCDE bit of the ECCR2/ECCR3 register is "1", the
clock output signal is delayed by the half of the serial clock cycle as shown in Figure 20.7-5.
The operation is prepared for communication devices which use the rising or falling edge of the serial clock
signal for the data sampling.
Transmission data
writing
Transmitting or
receiving clock
(normal)
Transmitting
clock (SCDE = 1)
Transmission and
reception data
If the SCES bit of the ESCR2/ESCR3 register is "1", the serial clock signal is inverted. Receiving data is
sampled at the falling edge of the serial clock.
If the MS bit of the ECCR2/ECCR3 register is "0" (master mode) and the SCKE bit of the SMR2/SMR3
register is "1" (clock output enabled), the output clock signal is also inverted.
While there is no communication, the clock signal must be kept at "0" as the mark level.
If the CCO bit of the ESCR2/ESCR3 register is "1", the serial clock is signaled even while there is no data
communication. Therefore it is recommended to specify the start/stop bits as shown in Figure 20.7-6.
reception or transmission clock
(SCES = 0, CCO = 1):
reception or transmission clock
(SCES = 1, CCO = 1):
data stream (SSM = 1)
(here: no parity, 1 stop bit)
386
Figure 20.7-5 Delayed Transmitting Clock Signal (SCDE=1)
Reception data sample edge (SCES = 0)
0 1
LSB
Figure 20.7-6 Continuous Clock Output in Mode 2
1 0 1 0 0
Data
ST
data frame
Mark level
Mark level
Mark level
1
MSB
SP