Fujitsu MB90390 Series Hardware Manual page 234

CHAPTER 13 16-BIT I/O TIMER
Table 13.4-1 Control Status Register of Output Compare (Lower)
Bit name
bit7 ICPm
bit6 ICPn
bit5 ICEm
bit4 ICEn
bit3, bit2 Undefined
bit1 CSTm
bit0 CSTn
n = 0, 2, 4, 6 m = 1, 3, 5, 7
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• These bits are used as output compare interrupt flags. "1" is set to these bits when the
compare register value matches the 16-bit free-run timer value. While the interrupt
request bits (ICEm and ICEn) are enabled, an output compare interrupt occurs when
the ICPm and ICPn bits are set. These bits are cleared by writing "0".
• "0": No compare match.
• "1": Compare match.
• Writing "1" has no effect.
• "1" is always read by a read-modify-write (RMW) instruction.
Note:
ICPn: Corresponds to output compare n.
ICPm: Corresponds to output compare m.
• These bits are used as output compare interrupt enable flags. While the "1" is written to
these bits, an output compare interrupt occurs when an interrupt flag (ICPm or ICPn) is
set.
• Writing "0": Output compare interrupt disabled.
• Writing "1": Output compare interrupt enabled.
Note:
ICEn: Corresponds to output compare unit n.
ICEm: Corresponds to output compare unit m.
• These bits are used to enable the compare register before the compare operation is
enabled
• Writing "0": Compare operation disabled.
• Writing "1": Compare operation enabled.
Note:
Ensure that a value is written to the compare register before the compare operation is
enabled.
CSTn: Corresponds to output compare n.
CSTm: Corresponds to output compare m.
Since output compare is synchronized with the 16-bit free-run timer clock, stopping
the 16-bit free-run timer stops compare operation.
Function
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