Fujitsu MB90390 Series Hardware Manual page 311

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A/D control status register (ADCS0, ADCS1)
This register selects activation by software or another activation trigger, the conversion mode, and the A/D
conversion channel. It also enables or disables interrupt requests, checks the interrupt request status, and
indicates whether the conversion has halted or is in progress.
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A/D data register (ADCR0, ADCR1)
This register holds the result of A/D conversion and selects the resolution for A/D conversion.
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Clock selector
The clock selector selects the clock for activating A/D conversion. Either 16-bit reload timer channel 1
output or external trigger (ADTG) can be used as the activation clock.
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Decoder
This circuit selects the analog input pin to be used based on the settings of the ANE0 to ANE2 bits and
ANS0 to ANS2 bits of the A/D control status register (ADCS0).
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Analog channel selector
This circuit selects the pin to be used from fifteen analog input pins.
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Sample hold circuit
This circuit maintains the input voltage of the channel selected by the analog channel selector. It samples
and maintains the input voltage obtained immediately after the activation of A/D conversion. This circuit
protects the A/D conversion from any variations in the input voltage during approximation.
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D/A converter
This circuit generates a reference voltage for comparison with the input voltage maintained by the sample
hold circuit.
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Comparator
This circuit compares the input voltage maintained by the sample hold circuit with the output voltage of the
D/A converter to determine which is greater.
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Control circuit
This circuit determines the A/D conversion value based on the decision signal generated by the comparator.
When the A/D conversion has been completed, the circuit sets the conversion result in the A/D data register
(ADCR0, ADCR1) and generates an interrupt request.
CHAPTER 18 8/10-BIT A/D CONVERTER
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