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20.8
Notes on Using UART2, UART3 ..................................................................................................... 401
2
21.1
C Interface Overview .................................................................................................................... 406
2
21.2
C Interface Registers ................................................................................................................... 408
21.2.1
Bus Status Register (IBSR) ....................................................................................................... 410
21.2.2
Bus Control Register (IBCR) ..................................................................................................... 413
21.2.3
Ten Bit Slave Address Register (ITBA) ..................................................................................... 422
21.2.4
Ten Bit Address Mask Register (ITMK) ..................................................................................... 423
2
21.2.5
I
C Seven Bit Slave Address Register (ISBA) ........................................................................... 425
2
21.2.6
C Data Register (IDAR) .......................................................................................................... 427
2
21.2.7
C Clock Control Register (ICCR) ............................................................................................ 428
21.2.8
Noise Filter Configuration Register (INFCR) ............................................................................. 431
2
21.3
C Interface Operation ................................................................................................................... 432
21.4
Programming Flow Charts .............................................................................................................. 435
CHAPTER 22 SERIAL I/O ............................................................................................... 437
22.1
Outline of Serial I/O ........................................................................................................................ 438
22.2
Serial I/O Registers ......................................................................................................................... 439
22.2.1
Serial Mode Control Status Register (SMCS) ........................................................................... 440
22.2.2
Serial Shift Data Register (SDR) ............................................................................................... 444
22.3
Serial I/O Prescaler (CDCR) ........................................................................................................... 445
22.4
Serial I/O Operation ........................................................................................................................ 446
22.4.1
Shift Clock ................................................................................................................................. 447
22.4.2
Serial I/O Operation ................................................................................................................... 448
22.4.3
Shift Operation Start/Stop Timing .............................................................................................. 450
22.4.4
Interrupt Function of the Extended Serial I/O Interface ............................................................. 453
CHAPTER 23 CAN CONTROLLER ................................................................................ 455
23.1
Features of CAN Controller ............................................................................................................ 456
23.2
Block Diagram of CAN Controller ................................................................................................... 457
23.3
List of Overall Control Registers ..................................................................................................... 458
23.4
List of Message Buffers (ID Registers) ........................................................................................... 460
23.5
List of Message Buffers (DLC Registers and Data Registers) ........................................................ 463
23.6
Classifying the CAN Controller Registers ....................................................................................... 466
23.6.1
Control Status Register (CSR) .................................................................................................. 467
23.6.2
Bus Operation Stop Bit (HALT = 1) ........................................................................................... 472
23.6.3
Last Event Indicator Register (LEIR) ......................................................................................... 474
23.6.4
Receive and Transmit Error Counters (RTEC) .......................................................................... 476
23.6.5
Bit Timing Register (BTR) .......................................................................................................... 477
23.6.6
Message Buffer Valid Register (BVALR) ................................................................................... 479
23.6.7
IDE register (IDER) .................................................................................................................... 480
23.6.8
Transmission Request Register (TREQR) ................................................................................ 481
23.6.9
Transmission RTR Register (TRTRR) ....................................................................................... 482
23.6.10 Remote Frame Receiving Wait Register (RFWTR) ................................................................... 483
23.6.11 Transmission Cancel Register (TCANR) ................................................................................... 484
23.6.12 Transmission Complete Register (TCR) .................................................................................... 485
2
C INTERFACE ......................................................................... 405
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