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15.2
Watch Timer Registers
The Watch Timer has the following five types of registers:
• Timer control register (WTCR)
• Subsecond register (WTBR)
• Second register (WTSR)
• Minute register (WTMR)
• Hour register (WTHR)
■ Watch Timer Registers
Timer control register
Address:
bit
000060
H
000061
H
Initial value:
Sub-second register (0)
Address:
bit
00354A
H
00354B
H
Initial value:
Second register/
Sub-second register (1)
Address:
bit
00354C
H
00354D
H
Initial value:
Hour Register/
Minute Register
Address:
bit
00354E
H
00354F
H
Initial value:
Notes:
• Clearing the clock counter affects the watchdog counter and interval interrupts that use clock
timer output.
• To clear the clock timer by writing "0" to the WTR bit in the clock timer control register (WTCR),
set the WTIE bit to "0" and set the clock timer to interrupt inhibited state. Before permitting an
interrupt, clear the interrupt request issued by writing "0" to the WTOF flag.
Figure 15.2-1 Watch Timer Registers
15
14
13
12
11
10
INTE3 INT3 INTE2 INT2 INTE1 INT1 INTE0 INT0
R/W
R/W R/W
R/W
R/W
R/W
0
0
0
0
0
0
15
14
13
12
11
10
D15
D14
D13
D12
D11
D10
R/W
R/W R/W
R/W
R/W
R/W
X
X
X
X
X
X
WTSR
15
14
13
12
11
10
-
-
S5
S4
S3
S2
-
-
R/W
R/W
R/W
R/W
X
X
X
X
X
X
WTHR
15
14
13
12
11
10
-
-
-
H4
H3
H2
-
-
-
R/W
R/W R/W
X
X
X
X
X
X
9
8
7
6
5
Reserved Reserved Reserved
R/W
R/W
R/W
R/W R/W
0
0
0
0
0
9
8
7
6
5
D9
D8
D7
D6
D5
R/W
R/W
R/W
R/W R/W
R/W
X
X
X
X
X
9
8
7
6
5
S1
S0
-
-
D21
D20
R/W
R/W
-
-
R/W
R/W
X
X
X
X
X
9
8
7
6
5
H0
H1
-
-
M5
M4
R/W
R/W
-
-
R/W
R/W
X
X
X
X
X
CHAPTER 15 WATCH TIMER
4
3
2
1
0
-
-
UPDT OE
ST
WTCR
-
-
R/W
R/W
R/W
X
X
0
0
0
4
3
2
1
0
WTBR0
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
X
X
X
X
X
WTBR1
4
3
2
1
0
D19
D18
D17
D16
R/W
R/W
R/W
R/W
X
X
X
X
X
WTMR
4
3
2
1
0
M3
M2
M1
M0
R/W
R/W
R/W
R/W
X
X
X
X
X
239
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