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MB90V390HA/MB90V390HB/MB90394HA: This paragraph is only relevant, if UART2, 3 operates in
If the bus (serial input) goes "0" (dominant) for more than 11 bit times, the LIN Break Detected (LBD) flag
bit of the Extended Status/Control Register (ESCR2/ESCR3) is set to "1". Note, that in this case after 9 bit
times the reception error flags are set to "1", therefore the RXE flag has to be set to "0", if only a LIN synch
break detect is desired.
The interrupt and the LBD flag are cleared after writing a "1" to the LBD flag. This has to be performed
before input capture interrupt for LIN synch field.
●
LIN Synchronization Field Edge Detection Interrupts
This paragraph is only relevant, if UART2, UART3 operates in mode 3 as a LIN slave. After a LIN synch
break detection the next falling edge of the reception bus is indicated by UART2, UART3. Simultaneously
an internal signal connected to the ICU1/ICU3/ICU5 is set to "1". This signal is reset to "0" after the fifth
falling edge of the LIN Synchronization Field. In both cases the ICU1/ICU3/ICU5 generates an interrupt, if
"both edge detection" and the ICU1/ICU3/ICU5 interrupt are enabled. The difference of the ICU1/ICU3/
ICU5 counter values is the serial clock multiplied by 8. Dividing it by 8 results in the new detected and
calculated baud rate for the dedicated reload counter. This value - 1 has then to be written to the Baud Rate
Generator Registers (BGR02/BGR03 and BGR12/BGR13).There is no need to restart the reload counter,
because it is automatically reset if a falling edge of a start bit is detected.
■ LIN-UART2, UART3 Interrupts and EI
Table 20.5-2 UART2, UART3 Interrupt and EI
Interrupt cause
UART2 reception
interrupt
UART2 transmission
interrupt
UART3 reception
interrupt
UART3 transmission
interrupt
2
*1: EI
OS service for UART2 reception is usable only if UART2 transmission interrupt and both of transmission and
reception interrupt of UART3 are disabled. When detecting receive errors, stop request for EI
2
*2: EI
OS service for UART2 transmission is usable only if UART2 reception interrupt and both of transmission and
reception interrupt of UART3 are disabled.
2
*3: EI
OS service for UART3 reception is usable only if UART3 transmission interrupt and both of transmission and
reception interrupt of UART2 are disabled. When detecting receive errors, stop request for EI
2
*4: EI
OS service for UART3 transmission is usable only if for UART3 reception interrupt and both of transmission and
reception interrupt of UART2 are disabled.
2
OS
2
OS
Interrupt control register
Interrupt
number
Register name
#39(27
)
ICR14
H
#40(28
)
ICR14
H
#39(27
)
ICR14
H
#40(28
)
ICR14
H
mode 3 as a LIN slave.
Vector table address
Address
Lower
0000BE
FFFF60
H
H
0000BE
FFFF5C
H
H
0000BE
FFFF60
H
H
0000BE
FFFF5C
H
H
CHAPTER 20 UART2, UART3
Upper
Bank
FFFF61
FFFF62
H
H
FFFF5D
FFFF5E
H
H
FFFF61
FFFF62
H
H
FFFF5D
FFFF5E
H
H
2
OS service is supported.
2
OS service is supported.
2
EI
OS
*1
*2
*3
*4
367
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