Fujitsu MB90390 Series Hardware Manual page 711

■ Write, Data Polling, Read (WE Control)
Third bus cycle
AQ18
7AAAA
to
H
AQ0
t
WC
CE
t
OE
t
WE
t
CS
DQ7
to
DQ0
t
DS
5.0 V
PA: Write address
PD: Write data
DQ7: Reverse output of write data
D : Output of write data
OUT
Note:
The last two bus cycle sequences out of the four are described.
Figure C-2 Write, Data Polling, Read (WE Control)
PA
t t
AS AH
GHWL
WP
t
WPH
t
DH
A0 PD
H
APPENDIX C Timing Diagrams in Flash Memory Mode
Data polling
PA
t
WHWH1
D
DQ7
OUT
t
RC
t
OE
t
DF
t
OH
t
CE
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