Fujitsu MB90390 Series Hardware Manual page 372

CHAPTER 20 UART2, UART3
■ Explanation of the Different Blocks
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Reload Counter
The reload counter functions as the dedicated baud rate generator. It can select external input clock or
internal clock for the transmitting and receiving clocks. The reload counter has a 15 bit register for the
reload value. The actual count of the transmission reload counter can be read via the BGR02/BGR12, resp.
BGR03/BGR13.
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Reception Control Circuit
The reception control circuit consists of a received bit counter, start bit detection circuit, and received
parity counter. The received bit counter counts reception data bits. When reception of one data item for the
specified data length is complete, the received bit counter sets the reception data register full flag in the
serial status register. The start bit detection circuit detects start bits from the serial input signal and sends a
signal to the reload counter to synchronize it to the falling edge of these start bits. The reception parity
counter calculates the parity of the reception data.
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Reception Shift Register
The reception shift register fetches reception data input from the SIN2/SIN3 pin, shifting the data bit by bit.
When reception is complete, the reception shift register transfers receive data to the RDR2/RDR3 register.
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Reception Data Register
This register retains reception data. Serial input data is converted and stored in this register.
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Transmission Control Circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and
transmission parity counter. The transmission bit counter counts transmission data bits. The transmission of
one data item of the specified data length is transmitted. When the transmission bit counter indicates the
transmission start of written data, the transmission data register full flag in the serial status register is set.
At this time, if the transmission interrupt is enabled, the transmission interrupt request is generated. The
transmission start circuit starts transmission when data is written to TDR2/TDR3. The transmission parity
counter generates a parity bit for data to be transmitted if parity is enabled.
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Transmission Shift Register
The transmission shift register transfers data written to the TDR2/TDR3 register to itself and outputs the
data to the SOT2/SOT3 pin, shifting the data bit by bit.
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Transmission Data Register (TDR2/TDR3)
This register sets transmission data. Data written to this register is converted to serial data and output.
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Error Detection Circuit
The error detection circuit checks if there was any error during the last reception. If an error has occurred it
sets the corresponding error flags.
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